EP1810LC-35

Product Summary

The EP1810LC-35 is an EPLD. It offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, the EP1810LC-35 also has a Turbo-only version. It supports 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The EP1810LC-35 provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. The EP1810LC-35 is available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.

Parametrics

EP1810LC-35 absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0V; (2)VI, DC input voltage: –2.0 to 7.0V; (3)IMAX, DC VCC or ground current: –175 to 175 mA; (4)IOUT DC output current, per pin: –25 to 25 mA; (5)TSTG, Storage temperature No bias: –65 to 150℃; (6)TAMB, Ambient temperature Under bias: –65 to 135℃; (7)TJ, Junction temperature Ceramic packages, under bias: 150℃; Plastic packages, under bias: 135℃.

Features

EP1810LC-35 features: (1)Device erasure and reprogramming with non-volatile EPROM configuration elements; (2)Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz; (3)24 to 68 pins available in dual in-line package (DIP), plastic J-lead; (4)chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages; (5)Programmable security bit for protection of proprietary designs; (6)100% generically tested to provide 100% programming yield; (7)Programmable registers providing D, T, JK, and SR flipflops with; (8)individual clear and clock controls; (9)Software design support featuring the Altera MAX+PLUS II; (10)development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems.

Diagrams